Mtocipc Communication; Messaging With Ipc Flags And Interrupts - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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C28x Memory Map
R/W
C28x
PIE PIE

1.12.3 MTOCIPC Communication

When a message is ready for the M3 to send to the C28x, the M3 can notify that to the C28x using
MTOCIPC flags or interrupts (flags 1-4). The C28x, upon polling for these MTOCIPC flags or upon getting
an MTOCIPC interrupt, can respond to the message sent by the M3. There are three 32-bit registers,
MTOCIPCSET, MTOCIPCCLR, and MTOCIPCFLG on the M3 memory map and two 32-bit registers,
MTOCIPCSTS and MTOCIPCACK, to implement the flag-based message communication from the M3 to
the C28x. The MTOCIPCSET register has 32 bits, each of which when set, is capable of enabling a
corresponding flag bit in the MTOCIPCFLG register on the M3 and a status bit in the MTOCIPCSTS
register on the C28x.
For example:
1. When the M3 wants to notify a message readiness to the C28x, the M3 can set bit 9 (IPC flag 10) in
the MTOCIPCSET register.
2. This action of the M3 will result in setting bit 9 in the MTOCIPCSTS register on the C28x along with bit
9 in the MTOCIPCFLG register on the M3. The MTOCIPCFLG register on the M3 and the
MTOCIPCSTS register on the C28x are physically the same, but named differently as the FLG register
on the M3 and the STS register on the C28x.
3. The C28x can poll for bit 9 (IPC flag 10) of the MTOCIPCSTS register while waiting for the message.
When bit 9 of the MTOCIPCSTS register gets set, the C28x can read the message if any or can take
necessary action depending on the design of the user's application.
4. Then the C28x should acknowledge the M3 that it received the MTOCIPC request by setting bit 9 of
the MTOCIPCACK register which will result in clearing bit 9 in the MTOCIPCFLG register and
MTOCIPCSTS register.
Note that the MTOCIPCCLR register on the M3 and the MTOCIPCACK register on the C28x are
physically the same, but named differently as the CLR register on the M3 and the ACK register on the
C28x.
SPRUHE8E – October 2012 – Revised November 2019
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Figure 1-25. Messaging with IPC Flags and Interrupts
C28 to M3 IPC
CTOMIPC CTOMIPC SET SET
CTOMIPC CTOMIPC CLR CLR
CTOMIPC CTOMIPC FLG FLG
M3 to C28 IPC M3 to C28 IPC
MTOCIPC MTOCIPC STS STS
MTOCIPC MTOCIPC ACK ACK
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Memory Map
Set Set Q Q
C28 to M3 IPC
Clear Clear
CTOMIPCACK CTOMIPCACK
CTOMIPCSTS CTOMIPCSTS
M3 to C28 IPC M3 to C28 IPC
MTOCIPCFLG MTOCIPCFLG
MTOCIPCCLR MTOCIPCCLR
Clear Clear
MTOCIPCSET MTOCIPCSET
Q Q Set Set
Inter Processor Communications (IPC)
NVIC NVIC
M3 M3
R/W
R/W
System Control and Interrupts
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