Input Qualifier Clock Cycles - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Table of Contents

C28 General-Purpose Input/Output (GPIO)

(IQSW) = 5 × t

If, for example, T

(IQSW) = 5 × 2 × 6.67 ns =66.7 ns.

To account for the asynchronous nature of the input relative to the sampling period and SYSCLKOUT,

up to an additional sampling period, t

input signal. For this example:

4-41, the glitch (A) is shorter then the qualification window and will be ignored by the input

A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to

0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in 2n

SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).

B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.

C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.

D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words,

the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. That would ensure 5 sampling periods for detection to occur. Since

external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.

General-Purpose Input/Output (GPIO)

(SP) = 5 × 2 × GPxCTRL[QUALPRDn] × T

= 6.67 ns, then the duration of the sampling window is:

= 333.4 ns + 66.67 ns = 400.1 ns

Figure 4-41. Input Qualifier Clock Cycles

GPxQSELn = 1,0 (6 samples)

Sampling Window

(SYSCLKOUT/2)

may be required to detect a change in the

Sampling Period determined

by GPxCTRL[QUALPRD]

(SYSCLKOUT cycle * 2 * QUALPRD) * 5

SPRUHE8E – October 2012 – Revised November 2019

or 5 × 2 × T

Submit Documentation Feedback

Chapters

Table of Contents