Table of Contents
Advertisement
Register Descriptions
11.8.2 Debug Control Register (DEBUGCTRL) — EALLOW Protected
The debug control register (DEBUGCTRL) is shown in
15
14
FREE
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-4. Debug Control Register (DEBUGCTRL) Field Descriptions
Bit
Field
15
FREE
14-0
Reserved
11.8.3 Revision Register (REVISION)
The revision register (REVISION) is shown in
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
15-8
TYPE
7-0
REV
966
C28 Direct Memory Access (DMA) Module
Figure 11-9. Debug Control Register (DEBUGCTRL)
Value
Description
Emulation Control Bit: This bit specifies the action when an emulation halt event occurs.
0
DMA runs until the current DMA read-write access is completed and the current status of a DMA is
frozen. See the HALT points in
1
DMA is unaffected by emulation suspend (run free)
Reserved
Figure 11-10. Revision Register (REVISION)
TYPE
R
Table 11-5. Revision Register (REVISION) Field Descriptions
Value
Description
DMA Type Bits. A type change represents a major functional feature difference in a peripheral
module. Within a peripheral type, there may be minor differences between devices which do not
affect the basic functionality of the module. These device-specific differences are listed in the
TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566).
0x0000
This document describes a Type0 DMA.
DMA Silicon Revision Bits: These bits specify the DMA revision and are changed if any bug
fixes are performed.
0x0000
First release
Copyright © 2012–2019, Texas Instruments Incorporated
Figure 11-9
and described in
Reserved
R-0
Figure 11-6
for possible halt states.
Figure 11-10
and described in
8
7
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Table
11-4.
Table
11-5.
REV
R
Submit Documentation Feedback
0
0
Advertisement
Chapters
Table of Contents
