Overwrite In The Transmitter; Proper Positioning Of Frame-Synchronization Pulses; Data In The Mcbsp Transmitter Overwritten And Thus Not Transmitted - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Figure 15-25. Proper Positioning of Frame-Synchronization Pulses
CLKR/CLKX
FSR/FSX

15.5.4 Overwrite in the Transmitter

As described in the section on McBSP transmission (page
data previously written to the DXR(s) by the CPU or DMA controller into the XSR(s) and then shift each bit
from the XSR(s) to the DX pin. If new data is written to the DXR(s) before the previous data is copied to
the XSR(s), the previous data in the DXR(s) is overwritten and thus lost.
15.5.4.1 Example of Overwrite Condition
Figure 15-26 shows what happens if the data in DXR1 is overwritten before being transmitted. Initially,
DXR1 is loaded with data C. A subsequent write to DXR1 overwrites C with D before C is copied to XSR1.
Thus, C is never transmitted on DX.
Figure 15-26. Data in the McBSP Transmitter Overwritten and Thus Not Transmitted
CLKX
FSX
A1 A0
DX
XRDY
15.5.4.2 Preventing Overwrites
You can prevent CPU overwrites by making the CPU:
• Poll for XRDY = 1 in SPCR2 before writing to the DXR(s). XRDY is set when data is copied from DXR1
to XSR1 and is cleared when new data is written to DXR1.
SPRUHE8E – October 2012 – Revised November 2019
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For 2-bit delay:
Next frame-synchronization
pulse here or later is OK.
DR/DX
B7 B6 B5
Write to DXR1(C) Write to DXR1(D)
Copyright © 2012–2019, Texas Instruments Incorporated
For 1-bit delay:
Next frame-synchronization
pulse here or later is OK.
For 0-bit delay:
Next frame-synchronization
pulse here or later is OK.
Earliest possible
time to begin transfer
of next frame
Last bit of
current frame
Section 15.3.6), the transmitter must copy the
B4 B3 B2 B1 B0
DXR1 to XSR1 Copy(D)
C28 Multichannel Buffered Serial Port (McBSP)
McBSP Exception/Error Conditions
D7 D6 D5
Write to DXR1(E)
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