32-Bit Cpu Timers 0/1/2; Cpu-Timers; Cpu-Timer Interrupts Signals And Output Signal - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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1.8.8 32-Bit CPU Timers 0/1/2

This section describes the three 32-bit CPU-timers (TIMER0/1/2) shown in
CPU Timer-0 and CPU-Timer 1 can be used in user applications. Timer 2 is reserved for DSP/BIOS. If the
application is not using DSP/BIOS, then Timer 2 can be used in the application. The CPU-timer interrupt
signals (TINT0, TINT1, TINT2) are connected as shown in
Reset
Timer reload
SYSCLKOUT
TCR.4
(Timer start status)
TINT
Figure 1-15. CPU-Timer Interrupts Signals and Output Signal
28x
CPU
A The timer registers are connected to the Memory Bus of the C28x processor.
B The timing of the CPU timers are synchronized to SYSCLKOUT of the processor clock.
SPRUHE8E – October 2012 – Revised November 2019
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Figure 1-14. CPU-Timers
16-bit timer divide-down
16-bit prescale counter
INT1
PIE
to
INT12
INT13
TINT2
INT14
Copyright © 2012–2019, Texas Instruments Incorporated
(Figure
Figure 1-15.
TDDRH:TDDR
PSCH:PSC
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TINT0
CPU TIMER 0
TINT1
CPU TIMER 1
CPU TIMER 2
(Reserved for DSP/BIOS)
System Control and Interrupts
Clock Control
1-14).
32-bit timer period
PRDH:PRD
32-bit counter
TIMH:TIM
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