Eqep Interrupt Generation; Qep Decoder Control (Qdecctl) Register; Eqep Decoder Control (Qdecctl) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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eQEP Interrupt Structure

shows how the interrupt mechanism works in the EQEP module.

Eleven interrupt events (PCE, PHE, QDC, WTO, PCU, PCO, PCR, PCM, SEL, IEL and UTO) can be

generated. The interrupt control register (QEINT) is used to enable/disable individual interrupt event

sources. The interrupt flag register (QFLG) indicates if any interrupt event has been latched and contains

the global interrupt flag bit (INT). An interrupt pulse is generated only to the PIE if any of the interrupt

events is enabled, the flag bit is 1 and the INT flag bit is 0. The interrupt service routine will need to clear

the global interrupt flag bit and the serviced event, via the interrupt clear register (QCLR), before any other

interrupt pulses are generated. You can force an interrupt event by way of the interrupt force register

(QFRC), which is useful for test purposes.

eQEP Registers

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-3. eQEP Decoder Control (QDECCTL) Register Field Descriptions

SPRUHE8E – October 2012 – Revised November 2019

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Figure 9-20. EQEP Interrupt Generation

Figure 9-21. QEP Decoder Control (QDECCTL) Register

Position-counter source selection

Quadrature count mode (QCLK = iCLK, QDIR = iDIR)

Direction-count mode (QCLK = xCLK, QDIR = xDIR)

UP count mode for frequency measurement (QCLK = xCLK, QDIR = 1)

DOWN count mode for frequency measurement

(QCLK = xCLK, QDIR = 0)

Sync output-enable

Disable position-compare sync output

Enable position-compare sync output

C28 Enhanced QEP (eQEP) Module

eQEP Interrupt Structure

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