Interrupt 0-31 Set Enable (En0) Register; Interrupt 0-31 Set Enable (En0) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

NVIC Register Descriptions
25.5 NVIC Register Descriptions
This section lists and describes the NVIC registers, in numerical order by address offset.
The NVIC registers can only be fully accessed from privileged mode, but interrupts can be appended while
in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any other
unprivileged mode access causes a bus fault.
Ensure software uses correctly aligned register accesses. The processor does not support unaligned
accesses to NVIC registers.
An interrupt can enter the pending state even if it is disabled.
Before programming the VTABLE register to relocate the vector table, ensure the vector table entries of
the new vector table are set up for fault handlers, NMI, and all enabled exceptions such as interrupts.
25.5.1 Interrupt 0-31 Set Enable (EN0) Register, offset 0x100
The Interrupt 0-31 Set Enable (EN0) register enables interrupts and shows which interrupts are enabled.
Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See the Cortex-M3 Processor chapter
for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not
enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates
the interrupt, regardless of its priority.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-11. Interrupt 0-31 Set Enable (EN0) Register Field Descriptions
Bit Field
31-0 INT
1648
Cortex-M3 Peripherals
Figure 25-5. Interrupt 0-31 Set Enable (EN0) Register
Value Description
Interrupt Enable
0 On a read, indicates the interrupt is disabled. On a write, no effect
1 On a read, indicates the interrupt is enabled. On a write, enables the interrupt.
A bit can only be cleared by setting the corresponding INT[n] bit in the DISn register.
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SPRUHE8E – October 2012 – Revised November 2019
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