Spiclk Signal Options; Spi: Spiclk-Clkout Characteristic When (Brr + 1) Is Odd, Brr > 3, And Clock Polarity = 1; Spi Clocking Scheme Selection Guide - Texas Instruments Concerto F28M36 Series Technical Reference Manual

www.ti.com
The selection procedure for the SPI clocking scheme is shown in
clocking schemes relative to transmitted and received data are shown in
SPICLK Scheme
Rising edge without delay
Rising edge with delay
Falling edge without delay
Falling edge with delay
(1)
The description of CLOCK PHASE and CLOCK POLARITY differs between manufacturers. For proper operation, select the
desired waveform to determine the PHASE and POLARITY settings.
SPICLK cycle
number
SPICLK
(Rising edge
without delay)
SPICLK
(Rising edge
with delay
)
SPICLK
(Falling edge
without delay)
SPICLK
(Falling edge
with delay)
SPISIMO/
See note
SPISOMI
SPISTE
(Into slave)
Receive latch
points
Note: Previous data bit
For the SPI, SPICLK symmetry is retained only when the result of (SPIBRR+1) is an even value. When
(SPIBRR + 1) is an odd value and SPIBRR is greater than 3, SPICLK becomes asymmetrical. The low
pulse of SPICLK is one CLKOUT longer than the high pulse when the CLOCK POLARITY bit is clear (0).
When the CLOCK POLARITY bit is set to 1, the high pulse of the SPICLK is one CLKOUT longer than the
low pulse, as shown in
Figure 12-5. SPI: SPICLK-CLKOUT Characteristic When (BRR + 1) is Odd, BRR > 3, and CLOCK
CLKOUT
SPICLK
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
Table 12-3. SPI Clocking Scheme Selection Guide
CLOCK POLARITY
Figure 12-4. SPICLK Signal Options
1 2 3
MSB
Figure 12-5.
POLARITY = 1
2 cycles
Copyright © 2012–2019, Texas Instruments Incorporated
Table 12-3. Examples of these four
Figure
(SPICCR.6)
0
0
1
1
4 5 6
3 cycles 2 cycles
C28 Serial Peripheral Interface (SPI)
Enhanced SPI Module Overview
12-4.
CLOCK PHASE
(1)
(SPICTL.3)
0
1
0
1
7 8
LSB
991