Pin Control Register (Pcr); Pin Control Register (Pcr) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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15.12.9 Pin Control Register (PCR)

Each McBSP has one pin control register (PCR).
enables you to:
• Choose a frame-synchronization mode for the transmitter (FSXM) and for the receiver (FSRM)
• Choose a clock mode for transmitter (CLKXM) and for the receiver (CLKRM)
• Select the input clock source for the sample rate generator (SCLKME, in conjunction with the CLKSM
bit of SRGR2)
• Choose whether frame-synchronization signals are active low or active high (FSXP for transmission,
FSRP for reception)
• Specify whether data is sampled on the falling edge or the rising edge of the clock signals (CLKXP for
transmission, CLKRP for reception)
The pin control register (PCR) is shown in
15
Reserved
7 6
SCLKME
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
15:12 Reserved
11 FSXM
10 FSRM
SPRUHE8E – October 2012 – Revised November 2019
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Figure 15-77
Figure 15-77. Pin Control Register (PCR)
12
R-0
4
Reserved
R-0
Table 15-86. Pin Control Register (PCR) Field Descriptions
Value Description
0 Reserved bit (not available for your use). It is a read-only bit and returns a 0 when read.
Transmit frame-synchronization mode bit. FSXM determines whether transmit frame-
synchronization pulses are supplied externally or internally. The polarity of the signal on the
FSX pin is determined by the FSXP bit.
0 Transmit frame synchronization is supplied by an external source via the FSX pin.
1 Transmit frame synchronization is generated internally by the Sample Rate generator, as
determined by the FSGM bit of SRGR2.
Receive frame-synchronization mode bit. FSRM determines whether receive frame-
synchronization pulses are supplied externally or internally. The polarity of the signal on the
FSR pin is determined by the FSRP bit.
0 Receive frame synchronization is supplied by an external source via the FSR pin.
1 Receive frame synchronization is supplied by the sample rate generator. FSR is an output pin
reflecting internal FSR, except when GSYNC = 1 in SRGR2.
Copyright © 2012–2019, Texas Instruments Incorporated
Table 15-86 describes the bits of PCR. This register
and described in Table
11 10
FSXM FSRM
R/W-0 R/W-0
3 2
FSXP FSRP
R/W-0 R/W-0
C28 Multichannel Buffered Serial Port (McBSP)
McBSP Registers
15-86.
9 8
CLKXM CLKRM
R/W-0 R/W-0
1 0
CLKXP CLKRP
R/W-0 R/W-0
1175