16-Bit Pwm Mode; Register Map; Timers Register Map - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting.
8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In
both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM Interrupt Clear
(GPTMICR) register. The time at which the event happened can be obtained by reading the GPTM
Timer n (GPTMTnR) register.
In Input Edge Timing mode, the timer continues running after an edge event has been detected, but the
timer interval can be changed at any time by writing the GPTMTnILR register. The change takes effect at
the next cycle after the write.

2.4.5 16-Bit PWM Mode

A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to 0x0, and
the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field of the
GPTM Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register.
6. Load the GPTM Timer n Match (GPTMTnMATCHR) register with the match value.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin generation of
the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The PWM
period can be adjusted at any time by writing the GPTMTnILR register, and the change takes effect at the
next cycle after the write.
2.5

Register Map

Table 2-4 lists the GPTM registers. The offset listed is a hexadecimal increment to the register 's address,
relative to that timer's base address:
• Timer 0: 0x4003.0000
• Timer 1: 0x4003.1000
• Timer 2: 0x4003.2000
• Timer 3: 0x4003.3000
Note that the GP Timer module clock must be enabled before the registers can be programmed (see the
RCGC1 register in the System Control chapter). Before any timer module registers are accessed, there
must be a delay of three system clocks after the timer module clock is enabled.
Offset
0x000
0x004
0x008
0x00C
0x018
0x01C
0x020
0x024
0x028
SPRUHE8E – October 2012 – Revised November 2019
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Table 2-4. Timers Register Map
Name Type
GPTMCFG R/W
GPTMTAMR R/W
GPTMTBMR R/W
GPTMCTL R/W
GPTMIMR R/W
GPTMRIS
GPTMMIS
GPTMICR W1C
GPTMTAILR R/W
Copyright © 2012–2019, Texas Instruments Incorporated
Reset
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
R 0x0000.0000
R 0x0000.0000
0x0000.0000
0xFFFF.FFFF
Initialization and Configuration
Description
GPTM Configuration
GPTM Timer A Mode
GPTM Timer B Mode
GPTM Control
GPTM Interrupt Mask
GPTM Raw Interrupt
Status
GPTM Masked Interrupt
Status
GPTM Interrupt Clear
GPTM Timer A Interval
Load
315
M3 General-Purpose Timers