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21.3.5 ISO 7816 Support
The UART offers basic support to allow communication with an ISO 7816 smartcard. When bit 3 (SMART)
of the UARTCTL register is set, the UnTx signal is used as a bit clock, and the UnRx signal is used as the
half-duplex communication line connected to the smartcard. A GPIO signal can be used to generate the
reset signal to the smartcard. The remaining smartcard signals should be provided by the system design.
When using ISO 7816 mode, the UARTLCRH register must be set to transmit 8-bit words (WLEN bits 6:5
configured to 0x3) with EVEN parity (PEN set and EPS set). In this mode, the UART automatically uses 2
stop bits, and the STP2 bit of the UARTLCRH register is ignored.
If a parity error is detected during transmission, UnRx is pulled Low during the second stop bit. In this
case, the UART aborts the transmission, flushes the transmit FIFO and discards any data it contains, and
raises a parity error interrupt, allowing software to detect the problem and initiate retransmission of the
affected data. Note that the UART does not support automatic retransmission in this case.
21.3.6 LIN Support
The UART module offers hardware support for the LIN protocol as either a master or a slave. The LIN
mode is enabled by setting the LIN bit in the UARTCTL register. A LIN message is identified by the use of
a Sync Break at the beginning of the message. The Sync Break is a transmission of a series of 0s. The
Sync Break is followed by the Sync data field (0x55).
message.
The UART should be configured as followed to operate in LIN mode:
•
Configure the UART for 1 start bit, 8 data bits, no parity, and 1 stop bit. Enable the Transmit FIFO.
•
Set the LIN bit in the UARTCTL register.
When preparing to send a LIN message, the TXFIFO should contain the Sync data (0x55) at FIFO
location 0 and the Identifier data at location 1, followed by the data to be transmitted, and with the
checksum in the final FIFO entry.
21.3.6.1 LIN Master
The UART is enabled to be the LIN master by setting the MASTER bit in the UARTLCTL register. The
length of the Sync Break is programmable using the BLEN field in the UARTLCTL register and can be 13-
16 bits (baud clock cycles).
21.3.6.2 LIN Slave
The LIN UART slave is required to adjust its baud rate to that of the LIN master. In slave mode, the LIN
UART recognizes the Sync Break, which must be at least 13 bits in duration. A timer is provided to
capture timing data on the 1st and 5th falling edges of the Sync field so that the baud rate can be adjusted
to match the master.
SPRUHE8E – October 2012 – Revised November 2019
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Figure 21-4. LIN Message
Message Frame
Header
Synch
Synch Field
Ident Field
Break
In-Frame
Response
Copyright © 2012–2019, Texas Instruments Incorporated
Figure 21-4
illustrates the structure of a LIN
Response
Data
Checksum
Data Field
Field(s)
Field
Interbyte
Space
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
Functional Description
1493
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