32-Bit Read; Adc Trigger - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Clock
Bus[7:0] Ready 2-3 Cycle Sync Stall
Size
R/W
Digital Buffer
Analog Buffer
Clock
Bus[7:0] Ready 2-3 Cycle Sync Stall
Size
R/W
Digital Buffer
Analog Buffer
Clock
Ready 2-3 Cycle Sync Stall
Bus[7:0]
Size
R/W
Digital Buffer
Analog Buffer
SPRUHE8E – October 2012 – Revised November 2019
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Figure 10-6. 32-bit Read
Addr Addr Word 1
Read Stall
15:8 7:0 15:8
Figure 10-7. 64-bit Read
Addr Addr Word 1
Read Stall
15:8 7:2 - 00 15:8
Figure 10-8. ADC Trigger
Trig Sync
7:0 Stall
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Analog Common Interface Bus (ACIB)
Word 1 Word 2 Word 2
Sync Stall
7:0 15:8 7:0
Word 1 Word 2 Word 2 Word 3 Word 3
7:0 15:8 7:0 15:8 7:0
Ready
Ready
Word 4 Word 4
Sync Stall Ready
15:8 7:0
Analog Subsystem
895