Gpio Port D Set, Clear And Toggle (Gpdset, Gpdclear, Gpdtoggle) Registers; Gpio Port D Set (Gpdset) Register Field Descriptions; Gpio Port D Clear (Gpdclear) Register Field Descriptions; Gpio Port D Toggle (Gpdtoggle) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

C28 General-Purpose Input/Output (GPIO)

4.2.7.48 GPIO Port D Set, Clear and Toggle (GPDSET, GPDCLEAR, GPDTOGGLE) Registers

The GPIO Port D Set, Clear and Toggle (GPBSET, GPDCLEAR, GPDTOGGLE) registers are shown and
described in the figure and table below.
Figure 4-89. GPIO Port D Set, Clear and Toggle (GPDSET, GPDCLEAR, GPDTOGGLE) Registers
31 30
GPIO127 GPIO126
R/W-x R/W-x
23 22
GPIO119 GPIO118
R/W-x R/W-x
15 14
GPIO111 GPIO110
R/W-x R/W-x
7 6
GPIO103 GPIO102
R/W-x R/W-x
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-104. GPIO Port D Set (GPDSET) Register Field Descriptions
Bits Field
31-0 GPIO127-GPIO96
Table 4-105. GPIO Port D Clear (GPDCLEAR) Register Field Descriptions
Bits Field
31-0 GPIO127-GPIO96
Table 4-106. GPIO Port D Toggle (GPDTOGGLE) Register Field Descriptions
Bits Field
31-0 GPIO127-GPIO96
456
General-Purpose Input/Output (GPIO)
29 28
GPIO125 GPIO124
R/W-x R/W-x
21 20
GPIO117 GPIO116
R/W-x R/W-x
13 12
GPIO109 GPIO108
R/W-x R/W-x
5 4
GPIO101 GPIO100
R/W-x R/W-x
Value
Each GPIO port D pin (GPIO127-GPIO96) corresponds to one bit in this register.
0 Writes of 0 are ignored. This register always reads back a 0.
1 Writing a 1 forces the respective output data latch to high. If the pin is configured as a GPIO
output then it will be driven high. If the pin is not configured as a GPIO output then the latch is
set but the pin is not driven.
Value
Each GPIO port D pin (GPIO127-GPIO96) corresponds to one bit in this register.
0 Writes of 0 are ignored. This register always reads back a 0.
1 Writing a 1 forces the respective output data latch to low. If the pin is configured as a GPIO
output then it will be driven low. If the pin is not configured as a GPIO output then the latch is
cleared but the pin is not driven.
Value
Each GPIO port D pin (GPIO127-GPIO96) corresponds to one bit in this register.
0 Writes of 0 are ignored. This register always reads back a 0.
1 Writing a 1 forces the respective output data latch to toggle from its current state. If the pin is
configured as a GPIO output then it will be driven in the opposite direction of its current state. If
the pin is not configured as a GPIO output then the latch is cleared but the pin is not driven.
Copyright © 2012–2019, Texas Instruments Incorporated
27 26
GPIO123 GPIO122
R/W-x R/W-x
19 18
GPIO115 GPIO114
R/W-x R/W-x
11 10
GPIO107 GPIO106
R/W-x R/W-x
3 2
GPIO99 GPIO98
R/W-x R/W-x
Description
Description
Description
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
25 24
GPIO121 GPIO120
R/W-x R/W-x
17 16
GPIO113 GPIO112
R/W-x R/W-x
9 8
GPIO105 GPIO104
R/W-x R/W-x
1 0
GPIO97 GPIO96
R/W-x R/W-x
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