Sci Registers; Sci Module Register Summary; Scia Registers; Scib Registers - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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13.3 SCI Registers

The functions of the SCI are software configurable. Sets of control bits, organized into dedicated bytes,
are programmed to initialize the desired SCI communications format. This includes operating mode and
protocol, baud value, character length, even/odd parity or no parity, number of stop bits, and interrupt
priorities and enables.

13.3.1 SCI Module Register Summary

The SCI is controlled and accessed through registers listed in
described in the sections that follow.
Register Mnemonic
SCICCR
SCICTL1
SCIHBAUD
SCILBAUD
SCICTL2
SCIRXST
SCIRXEMU
SCIRXBUF
SCITXBUF
(1)
SCIFFTX
(1)
SCIFFRX
(1)
SCIFFCT
SCIPRI
(1)
These registers operate in enhanced mode.
Name
SCICCR
SCICTL1
SCIHBAUD
SCILBAUD
SCICTL2
SCIRXST
SCIRXEMU
SCIRXBUF
SCITXBUF
SCIFFTX
SCIFFRX
SCIFFCT
SCIPRI
SPRUHE8E – October 2012 – Revised November 2019
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Table 13-7. SCIA Registers
Address
Number of Bits
0x0000-7050
0x0000-7051
0x0000-7052
0x0000-7053
0x0000-7054
0x0000-7055
0x0000-7056
0x0000-7057
0x0000-7059
0x0000-705A
0x0000-705B
0x0000-705C
0x0000-705F
Table 13-8. SCIB Registers
Address Range
Number of Bits
0x0000-7750
0x0000-7751
0x0000-7752
0x0000-7753
0x0000-7754
0x0000-7755
0x0000-7756
0x0000-7757
0x0000-7759
0x0000-775A
0x0000-775B
0x0000-775C
0x0000-775F
Copyright © 2012–2019, Texas Instruments Incorporated
Table 13-7
and
Description
1
SCI-A Communications Control Register
1
SCI-A Control Register 1
1
SCI-A Baud Register, High Bits
1
SCI-A Baud Register, Low Bits
1
SCI-A Control Register 2
1
SCI-A Receive Status Register
1
SCI-A Receive Emulation Data Buffer Register
1
SCI-A Receive Data Buffer Register
1
SCI-A Transmit Data Buffer Register
1
SCI-A FIFO Transmit Register
1
SCI-A FIFO Receive Register
1
SCI-A FIFO Control Register
1
SCI-A Priority Control Register
Description
1
SCI-B Communications Control Register
1
SCI-B Control Register 1
1
SCI-B Baud Register, High Bits
1
SCI-B Baud Register, Low Bits
1
SCI-B Control Register 2
1
SCI-B Receive Status Register
1
SCI-B Receive Emulation Data Buffer Register
1
SCI-B Receive Data Buffer Register
1
SCI-B Transmit Data Buffer Register
1
SCI-B FIFO Transmit Register
1
SCI-B FIFO Receive Register
1
SCI-B FIFO Control Register
1
SCI-B Priority Control Register
C28 Serial Communications Interface (SCI)
SCI Registers
Table
13-8, which are
1031

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