Pie Interrupt Sources And External Interrupts Xint1/Xint2/Xint3 - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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1.5.4.3 Interrupt Sources
Figure 1-7 shows how the various interrupt sources are multiplexed within the devices. This multiplexing
(MUX) scheme may not be exactly the same on all 28x devices. See the device data manual for details.
Figure 1-7. PIE Interrupt Sources and External Interrupts XINT1/XINT2/XINT3
INT1
to
INT12
C28
Core
INT13
INT14
NMI
1.5.4.3.1 Procedure for Handling Multiplexed Interrupts
The PIE module multiplexes eight peripheral and external pin interrupts into one CPU interrupt. These
interrupts are divided into 12 groups: PIE group 1 - PIE group 12. Each group has an associated enable
PIEIER and flag PIEIFR register. These registers are used to control the flow of interrupts to the CPU. The
PIE module also uses the PIEIER and PIEIFR registers to decode to which interrupt service routine the
CPU should branch.
SPRUHE8E – October 2012 – Revised November 2019
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WAKEINT
U
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T
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P 9
I 6
E
I
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p
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TINT1
TINT2
NMI Interrupt With Watchdog Function
Copyright © 2012–2019, Texas Instruments Incorporated
Sync
SYSCLKOUT
XINT1
Interrupt Control
XINT1 CR (15:0)
XINT1 CTR (15:0)
XINT2
Interrupt Control
XINT2CR(15:0)
XINT2CTR(15:0)
XINT3
Interrupt Control
XINT3CR(15:0)
XINT3CTR(15:0)
TINT0
CPU TIMER0
CPU TIMER1
CPU TIMER2
NMIRS
Exceptions and Interrupts Control
Peripherals
WDINT
Watchdog
LPMINT
Low Power Modes
M
XINT1
U
X
GPTRIP4SEL(5:0)
M
XINT2
U
X
GPTRIPSEL(5:0)
M
XINT3
U
X
GPIO63. int
GPTRIPSEL(5:0)
TOUT1
Flash Wrapper
CPUTMR2CLK
System Control
System Control and Interrupts
GPIO0 .int
GPIO
Mux
107