Gpio Port B Direction (Gpbdir) Register; Gpio Port A Direction (Gpadir) Register Field Descriptions; Gpio Port B Direction (Gpbdir) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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C28 General-Purpose Input/Output (GPIO)
Table 4-80. GPIO Port A Direction (GPADIR) Register Field Descriptions
Bits
Field
31-0
GPIO31-GPIO0
(1)
This register is EALLOW protected.

4.2.7.31 GPIO Port B Direction (GPBDIR) Register

The GPIO Port B Direction (GPBDIR) register is shown and described in the figure and table below.
31
30
GPIO63
GPIO62
R/W-0
R/W-0
23
22
GPIO55
GPIO54
R/W-0
R/W-0
15
14
GPIO47
GPIO46
R/W-0
R/W-0
7
6
GPIO39
GPIO38
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-81. GPIO Port B Direction (GPBDIR) Register Field Descriptions
Bits
Field
31-0
GPIO63-GPIO32
(1)
This register is EALLOW protected.
4.2.7.32 GPIO Port C Direction (GPCDIR) Register
The GPIO Port C Direction (GPCDIR) Register is shown and described in the figure and table below.
442
General-Purpose Input/Output (GPIO)
Value
Controls direction of GPIO Port A pins when the specified pin is configured as a GPIO in the
appropriate GPAMUX1 or GPAMUX2 register.
0
Configures the GPIO pin as an input. (default)
1
Configures the GPIO pin as an output
The value currently in the GPADAT output latch is driven on the pin. To initialize the GPADAT
latch prior to changing the pin from an input to an output, use the GPASET, GPACLEAR, and
GPATOGGLE registers.
Figure 4-72. GPIO Port B Direction (GPBDIR) Register
29
28
GPIO61
GPIO60
R/W-0
R/W-0
21
20
GPIO53
GPIO52
R/W-0
R/W-0
13
12
GPIO45
GPIO44
R/W-0
R/W-0
5
4
GPIO37
GPIO36
R/W-0
R/W-0
Value
Controls direction of GPIO pin when GPIO mode is selected. Reading the register returns the
current value of the register setting
0
Configures the GPIO pin as an input. (default)
1
Configures the GPIO pin as an output
Copyright © 2012–2019, Texas Instruments Incorporated
(1)
Description
27
26
GPIO59
GPIO58
R/W-0
R/W-0
19
18
GPIO51
GPIO50
R/W-0
R/W-0
11
10
GPIO43
GPIO42
R/W-0
R/W-0
3
2
GPIO35
GPIO34
R/W-0
R/W-0
(1)
Description
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
25
24
GPIO57
GPIO56
R/W-0
R/W-0
17
16
GPIO49
GPIO48
R/W-0
R/W-0
9
8
GPIO41
GPIO40
R/W-0
R/W-0
1
0
GPIO33
GPIO32
R/W-0
R/W-0
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