Ethernet Mac Threshold (Macthr) Register; Ethernet Mac Threshold (Macthr) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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19.6.8 Ethernet MAC Threshold (MACTHR) Register, offset 0x01C
In order to increase the transmission rate, it is possible to program the Ethernet MAC to begin
transmission of the next frame prior to the completion of the transmission of the current frame. Caution –
Extreme care must be used when implementing this function. Software must be able to guarantee that the
complete frame is able to be stored in the transmission FIFO prior to the completion of the transmission
frame. This register enables software to set the threshold level at which the transmission of the frame
begins. If the THRESH bits are set to 0x3F, which is the reset value, the early transmission feature is
disabled, and transmission does not start until the NEWTX bit is set in the MACTR register.
Writing the THRESH field to any value besides 0x3F enables the early transmission feature. Once the
byte count of data in the TX FIFO reaches the value derived from the THRESH bits as shown below,
transmission of the frame begins. When the THRESH field is clear, transmission of the frame begins after
4 bytes (a single write) are stored in the TX FIFO. Each increment of the THRESH bit field waits for an
additional 32 bytes of data (eight writes) to be stored in the TX FIFO. Therefore, a value of 0x01 causes
the transmitter to wait for 36 bytes of data to be written while a value of 0x02 makes the wait equal to 68
bytes of written data. In general, early transmission starts when:
Number of Bytes ≥ 4 ((THRESH x 8) + 1)
Reaching the threshold level has the same effect as setting the NEWTX bit in the MACTR register.
Transmission of the frame begins, and then the number of bytes indicated by the Data Length field is
transmitted. Because underrun checking is not performed, if any event, such as an interrupt, delays the
filling of the FIFO, the tail pointer may reach and pass the write pointer in the TX FIFO. In this event,
indeterminate values are transmitted rather than the end of the frame. Therefore, sufficient bus bandwidth
for writing to the TX FIFO must be guaranteed by the software.
If a frame smaller than the threshold level must be sent, the NEWTX bit in the MACTR register must be
set with an explicit write, which initiates the transmission of the frame even though the threshold limit has
not been reached.
If the threshold level is set too small, it is possible for the transmitter to underrun. If this occurs, the
transmit frame is aborted, and a transmit error occurs. Note that in this case, the TXER bit in the MACRIS
is not set, meaning that the CPU receives no indication that a transmit error happened.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-11. Ethernet MAC Threshold (MACTHR) Register Field Descriptions
Bit Field
31-6 Reserved
5-0 THRESH
SPRUHE8E – October 2012 – Revised November 2019
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Figure 19-12. Ethernet MAC Threshold (MACTHR) Register
R-0
Value Description
Reserved
Threshold Value
3Fh The THRESH bits represent the early transmit threshold. Once the amount of data in the TX FIFO
exceeds the value represented by the above equation, transmission of the packet begins.
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R-0
6 5
M3 Ethernet Media Access Controller (EMAC)
Ethernet MAC Register Descriptions
THRESH
R/W-1
16
0
1433