Effects Of Dlb And Clkstp On Clock Modes; Choosing An Input Clock For The Sample Rate Generator With The Sclkme And Clksm Bits - Texas Instruments Concerto F28M36 Series Technical Reference Manual

McBSP Sample Rate Generator
15.4.1.1 Clock Generation in the Sample Rate Generator
The sample rate generator can produce a clock signal (CLKG) for use by the receiver, the transmitter, or
both. Use of the sample rate generator to drive clocking is controlled by the clock mode bits (CLKRM and
CLKXM) in the pin control register (PCR). When a clock mode bit is set to 1 (CLKRM = 1 for reception,
CLKXM = 1 for transmission), the corresponding data clock (CLKR for reception, CLKX for transmission)
is driven by the internal sample rate generator output clock (CLKG).
The effects of CLKRM = 1 and CLKXM = 1 on the McBSP are partially affected by the use of the digital
loopback mode and the clock stop (SPI) mode, respectively, as described in
loopback mode (described in
(described in Section
When using the sample rate generator as a clock source, make sure the sample rate generator is enabled
(GRST = 1).
Mode Bit Settings
CLKRM = 1 DLB = 0
(Digital loopback mode disabled)
DLB = 1
(Digital loopback mode enabled)
CLKXM = 1 CLKSTP = 00b or 01b
(Clock stop (SPI) mode disabled)
CLKSTP = 10b or 11b
(Clock stop (SPI) mode enabled)
15.4.1.2 Choosing an Input Clock
The sample rate generator must be driven by an input clock signal from one of the three sources
selectable with the SCLKME bit of PCR and the CLKSM bit of SRGR2 (see
1, the minimum divide down value in CLKGDV bits is 1. CLKGDV is described in
Table 15-5. Choosing an Input Clock for the Sample Rate Generator with the
SCLKME
0
0
1
1
15.4.1.3 Choosing a Polarity for the Input Clock
As shown in Figure
input clock. The rising edge of CLKSRG generates CLKG and FSG, but you can determine which edge of
the input clock causes a rising edge on CLKSRG. The polarity options and their effects are described in
Table 15-6.
1088
C28 Multichannel Buffered Serial Port (McBSP)
Section 15.8.4) is selected with the DLB bit of SPCR1. The clock stop mode
15.7.2) is selected with the CLKSTP bits of SPCR1.
Table 15-4. Effects of DLB and CLKSTP on Clock Modes
SCLKME and CLKSM Bits
CLKSM Input Clock for Sample Rate Generator
0 Reserved
1 LSPCLK
0 Signal on MCLKR pin
1 Signal on MCLKX pin
15-18, when the input clock is received from a pin, you can choose the polarity of the
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Effect
CLKR is an output pin driven by the sample rate generator output clock
(CLKG).
CLKR is an output pin driven by internal CLKX. The source for CLKX
depends on the CLKXM bit.
CLKX is an output pin driven by the sample rate generator output clock
(CLKG).
The McBSP is a master in an SPI system. Internal CLKX drives internal
CLKR and the shift clocks of any SPI-compliant slave devices in the
system. CLKX is driven by the internal sample rate generator.
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Table 15-4. The digital
Table 15-5). When CLKSM =
Section 15.4.1.4.
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