Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1330

MSI Data Transfer Modes
Stream Data Transmit
If the MSI_CMD.XFRMODE bit =1, it is a stream-write data transfer. The data path pops the FIFO from the BIU
and transmits in a stream to the card data bus. If the FIFO becomes empty, the card clock is stopped and restarted
once data is available in the FIFO.
If the MSI_BYTCNT register is programmed to 0, it is an open-ended stream-write data transfer. During this data
transfer, the data path continuously transmits data in a stream until the host software issues a stop command. A
stream data transfer is terminated when the end bit of the stop command and end bit of the data match over two
clocks.
If the MSI_BYTCNT register is programmed with a non-zero value and the MSI_CMD.SENDASTOP bit is set, the
stop command is internally generated. The command is loaded in the command path when the end bit of the stop
command occurs after a match with the last byte of the stream-write transfer. This data transfer can also terminate if
the software issues a stop command before all the data bytes transfer to the card bus.
Single Block Data
If the MSI_CMD.XFRMODE bit =0 and the
register, a single-block write-data transfer occurs. The data transmit state machine sends data in a
MSI_BLKSIZ
single block, where the number of bytes equals the block size, including the internally-generated CRC16.
If the register bit is set for a 1-bit, 4-bit, or 8-bit data transfer, the data transmits on 1, 4, or 8 data
MSI_CTYPE
lines, respectively. CRC16 is separately generated and transmitted for 1, 4, or 8 data lines, respectively.
After a single data block is transmitted, the data transmit state machine receives the CRC status from the card and
signals a data transfer to the BIU. This operation happens when the MSI_ISTAT.DTO bit =1. If a negative CRC
status is received from the card, the data path signals a data CRC error to the BIU by setting the
MSI_ISTAT.DCRC bit.
Additionally, if the start bit of the CRC status is not received before two clocks after the end of the data block, a
CRC status start bit error is signaled to the BIU. The MSI_ISTAT.EBE bit is set.
Multiple Block Data
A multiple-block write-data transfer occurs if the MSI_CMD.XFRMODE bit =0 and the value in the
register is not equal to the value of the
blocks, where the number of bytes in a block equals the block size, including the internally-generated CRC16.
If the MSI_CTYPE register bit is set to 1-bit, 4-bit, or 8-bit data transfer, the data transmits on 1, 4, or 8 data lines,
respectively. CRC16 is separately generated and transmitted on 1, 4, or 8 data lines, respectively.
After one data block is transmitted, the data transmit state machine receives the CRC status from the card. If the
remaining MSI_BYTCNT
ation happens when the MSI_ISTAT.DTO bit =1. If the remaining data bytes are greater than 0, the data path
state machine starts to transmit another data block.
26–24
MSI_BYTCNT
MSI_BLKSIZ
becomes 0, the data path signals to the BIU that the data transfer is complete. This oper-
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register value is equal to the value of the
register. The data transmit state machine sends data in
MSI_BYTCNT