Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1331

If a negative CRC status is received from the card, the data path signals a data CRC error to the BIU by setting the
MSI_ISTAT.DCRC bit. The block continues further data transmission until all the bytes are sent. Additionally, if
the CRC status start bit is not received within two clocks after the end of a data block, a CRC status start bit error is
signaled to the BIU. The MSI_ISTAT.EBE bit is set. Further data transfer is terminated.
If the MSI_CMD.SENDASTOP is set, the stop command is internally generated during the transfer of the last data
block. No extra bytes are transferred to the card. The end bit of the stop command does not always exactly match
the end bit of the CRC status in the last data block.
If the block size is less than 4, 16, or 32 for card data widths of 1 bit, 4 bits, or 8 bits, respectively, the data transmit
state machine terminates the data transfer when all the data has transferred. The internally generated stop command
is loaded in the command path.
If the register =0 (the block size must be greater than 0), it is an open-ended block transfer. The data
MSI_BYTCNT
transmit state machine for this type of data transfer continues the block-write data transfer until the host software
issues a stop or abort command.
Data Receive
The data-receive state machine receives data two clock cycles after the end bit of a data read command, even if the
command path detects a response error or response CRC error. See the Data Receive State Machine figure. If a re-
sponse is not received from the card because a timeout error occurs, the BIU does not receive the signal that the data
transfer is complete. This error happens when the command sent by the MSI is an illegal operation for the card. The
error prevents the card from starting a read data transfer.
If data is not received before the data timeout, the data path signals a data timeout to the BIU and an end to the
data transfer done. Based on the value of the MSI_CMD.XFRMODE bit, the data-receive state machine gets data
from the card data bus in a stream or blocks.
Figure 26-9: Data Receive State Machine
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
LOAD_NEW_CMD
AND DATA EXPECTED
AND READ DATA
AND BLOCK TRANSFER
STOP DATA
COMMAND
RX DATA
BLOCK
BLOCK BYTE COUNT
DONE REMAINING !=0
STOP DATA
DATA RX
COMMAND
IDLE
RX DATA
STREAM
LOAD_NEW_CMD
AND DATA EXPECTED
AND READ DATA
AND STREAM TRANSFER
BYTE COUNT
REMAINING =0
OR STOP DATA
COMMAND
READ
WAIT
MSI Data Transfer Modes
26–25