Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1323

• Internally generated auto-stop command when the data path ends, the stop command request is loaded.
• IRQ response with RCA =0x000 when the command path is waiting for an IRQ response from the MMC
card, then the MSI_CTL.IRQRESP bit is set.
Loading a new command from the BIU in the command path depends on the following
tings:
• Update clock registers only using the MSI_CMD.UCLKREGS bit. If the MSI_CMD.UCLKREGS bit =1, the
command path updates only the clock enable and clock divider registers. If MSI_CMD.UCLKREGS =0, the
command path loads the command, command argument, and timeout registers, then starts processing the new
command.
• Wait for previous data to complete using the MSI_CMD.WTPRIVDATA bit. If the
MSI_CMD.WTPRIVDATA bit =1, the command path loads the new command under one of the following
conditions:
• Immediately, if the data path is free (that is, there is no data transfer in progress), or if an open-ended data
transfer is in progress
• After completion of the current data transfer, if a predefined data transfer is in progress.
Send Command and Receive Response
Once a new command is loaded in the command path with MSI_CMD.UCLKREGS bit =0, the command path
state machine sends out a command on the SD/MMC bus. The SD_MMC Command Path State Machine figure
illustrates the command path state machine.
Figure 26-7: SD_MMC Command Path State Machine
The command path state machine performs the following functions, according to following command register bit
values:
1. MSI_CMD.SENDINIT (send initialization). Initialization sequence of 80 clocks is sent before sending the
command.
2. MSI_CMD.RXPECT (response expected). A response is expected for the command. After the command is sent
out, the command path state machine receives a 48-bit or 136-bit response and sends it to the BIU. If the start
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
(MSI_BYTCNT =0).
LOAD_NEW_CMD
RESPONSE EXPECTED = 0
TRANSMIT
COMMAND
RESPONSE EXPECTED = 1
COMMAND
IDLE
t NCC DONE
WAIT_TNCC
SEND IRQ
RESPONSE
REQUEST
RESPONSE DONE/
RECEIVE
RESPONSE TIMEOUT
RESPONSE
Card Interface Unit
MSI_CMD register bit set-
26–17