Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1337

1. Before disabling the clocks, ensure that the card is not busy due to any previous data command. To determine
this status, check for 0 in the MSI_STAT.DBUSY bit.
2. Update the MSI_CLKEN
this update, send a command to the CIU to update the clock registers by setting the MSI_CMD.STARTCMD
bit, the MSI_CMD.WTPRIVDATA bits, and the MSI_CMD.UCLKREGS bit.
3. Set the MSI_CMD.STARTCMD bit to update the clock divider register, and send a command to the CIU in
order to update the clock registers. Wait for the CIU to take the command.
4. Set the MSI_CMD.STARTCMD to update the
command to the CIU to update the clock registers. Wait for the CIU to take the command.
If the software issues a controller reset command by setting the MSI_CTL.CTLRST bit, all the CIU state machines
are reset and the FIFO is not cleared. The DMA sends all remaining bytes to the host. In addition to a card-reset, if
a FIFO reset is also issued (MSI_CTL.FIFORST), then:
• Any pending DMA transfer on the bus completes correctly
• DMA data reads are ignored
• Write data is unknown (x)
Additionally, if a DMA reset is also issued (MSI_CTL.DMARST), any pending DMA transfer is abruptly termina-
ted.
If any of the previous data commands do not properly terminate, then the software must issue the FIFO reset. The
reset removes any residual data, if any, in the FIFO. After asserting the FIFO reset, the program waits until this bit is
cleared. One data transfer requirement between the FIFO and host is that the number of transfers must be a multi-
ple of the FIFO data width. For example, if the FIFO data width = 32-bit and the program must write only 15 bytes
to the card, the host must program the DMA to do 16-byte transfers to the card. (The program writes to the card
using the
MSI_BYTCNT
Initializing the MSI
After the power-up, the MSI is reset. The reset initializes the registers, ports, FIFO-pointers, DMA interface con-
trols, and state-machine. After power-on reset, the software performs the following steps which are reflected in the
Data Transmit State Machine figure.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register to disable all clocks. To ensure completion of any previous command before
register.)
register to enable the required clocks and send a
MSI_CLKEN
MSI Programming Model
26–31