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Core Registers
Mode Control 1 Register (MODE1)
The mode control 1 register is a non memory-mapped, universal, system
register (
and
Ureg
tion for the
MODE1
CBUFEN
Circular Buffer Addressing Enable
BDCST1
Broadcast Register Loads Indexed With I1 Enable
BDCST9
Broadcast Register Loads Indexed With I9 Enable
15 14 13 12 11 10
0
TRUNC
Truncation Rounding Mode
Select
SSE
Fixed-point Sign Extension
Select
ALUSAT
ALU Saturation Select
IRPTEN
Global Interrupt Enable
NESTM
Nesting Multiple Interrupts Enable
SRRFL
Secondary Registers Register File
Low Enable
SRRFH
Secondary Registers Register File High Enable
Figure A-1. Mode Control 1 Register
A-4
).
Figure A-1
Sreg
register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
9
8
0
0
0
0
0
0
0
ADSP-2126x SHARC Processor Hardware Reference
and
Table A-3
provide bit informa-
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RND32
Rounding for 32-Bit Float-
ing-Point Data Select
PEYEN
Processor Element Y Enable
BR8
Bit-Reverse Addressing for I8
BR0
Bit-Reverse Addressing for I0
SRCU
Secondary Registers Computa-
tional Units Enable
SRD1H
Secondary Registers DAG1
High Enable
SRD1L
Secondary Registers DAG1
Low Enable
SRD2H
Secondary Registers DAG2
High Enable
SRD2L
Secondary Registers DAG2
Low Enable
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