Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 404

SPORT Control Registers and Data Buffers
This description applies only to DSP Standard Serial mode and Multi-
channel modes only.
Serial Word Endian Select.
endian words (LSB first, if set, = 1) or big endian words (MSB first, if
cleared, = 0). This description applies to DSP Standard Serial And Multi-
channel modes only.
Serial Word Length Select.
word length in bits. Word sizes can be from 3 bits (
( = 31). This bit applies to all operation modes.
SLEN
Use this formula to calculate the value for
= Actual serial word length – 1
SLEN
In this case, the
Pair word length is limited to 8-32 bits, and DSP Standard mode word
length varies from 3 to 32 bits.
16-bit to 32-bit Word Packing Enable.
enables (if set, = 1) or disables (if cleared, = 0) 16- to 32-bit word packing.
This bit applies to all operation modes.
Internal Clock Select.
set, =1) or external (if cleared, =0) transmit or receive clock. This bit
applies to DSP Standard Serial mode and SPORTs 1, 3 and 5 for multi-
channel modes.
Sport Operation Mode.
2
I S/Left-justified Sample Pair modes if set (= 1), or disables if cleared
(= 0). This bit applies to all operation modes. See
and "Standard DSP Serial Mode" on page
9-54
SPCTLx
SPCTLx
bit cannot equal 0 or 1, I
SLEN
bit 10 (
SPCTLx
bit 11 (
SPCTLx
ADSP-2126x SHARC Processor Hardware Reference
Bit 3 ( ). This bit selects little
LSBF
Bit 8–4 ( ). These bits select the
SLENx
SLEN
:
SLEN
2
S, Left-justified Sample
bit 9 (
SPCTLx
). This bit selects the internal (if
ICLK
). This bit enables
OPMODE
Table 9-1 on page 9-10
9-11.
= 2) to 32 bits
). This bit
PACK