Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 689

Table A-22. PMCTL Register Bit Descriptions
Bits Name
5–0 PLLM
7:6 PLLDx
8 INDIV
9 DIVEN
11–10 Reserved
12 CLKOUTEN
14–13 Reserved
15 PLLBP
ADSP-2126x SHARC Processor Hardware Reference
Definition
PLL Multiplier. Read/Write
PLLM = 0 PLL Multiplier = 64
0<PLLM<63 PLL Multiplier = PLLM
CLK_CFG[1:0] Reset Value
00 = 0000110
01 = 100000
10 = 010000
11 = 000110
PLL Divider. Read/Write
00 = CK divider = 2
01 = CK divider = 4
10 = CK divider = 8
11 = CK divider = 16
CLK_CFG[1:0] Reset Value x x 00
Input Divisor. Read/Write
0 = divide by 1
1 = divide by 2
Reset Value = 0
Enable PLL Divider Value Loading. Read/Write
0 = Do not load PLLDx
1 = Load PLLDx
Reset Value = 0
Clockout Enable. Read/Write (Use for debug only)
Mux select for CLKOUT and RESETOUT
0 Mux output = RESETOUT
1 Mux output = CLKOUT
Reset Value = 0
PLL Bypass Mode Indication. Read/Write
0 = PLL is in normal mode
1 = Put PLL in bypass mode
Reset Value = 0
Registers Reference
A-67