Sport Divisor Registers (Divx - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

I/O Processor Registers

SPORT Divisor Registers (DIVx)

The addresses of the
DIV0 – 0xc02
DIV2 – 0x402
DIV4 – 0x802
The reset value for these registers is undefined. These registers contain two
fields:
• Bits 15–1 are
value for internally-generated
• Bits 31–16 are
internally-generated
CLKDIV
Clock Divisor
Figure A-27. DIVx Register
A-86
registers are:
DIVx
DIV1 – 0xc03
DIV3 – 0x403
DIV5 – 0x803
. These bits identify the Serial Clock Divisor
CLKDIV
CLKDIV =
. These bits select the Frame Sync Divisor for
FSDIV
as follows:
TFS
31 30 29 28 27 26 25
0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
FSDIV
ADSP-2126x SHARC Processor Hardware Reference
as follows:
SCLK
f
CCLK
-------------------- - 1
–
 
4 f
SCLK
24 23 22 21 20 19 18 17 16
0 0 1 0 0 0 0 0
7 6 5 4 3 2 1
0 1 0 0 0 0 0
f
SCLK
------------ 1
–
=
f
SFS
0
FSDIV
Frame Sync Divisor
0
0
Reserved