Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 406

SPORT Control Registers and Data Buffers
Serial Port DMA Chaining Enable.
). These bits enable (if set, = 1) or disables (if cleared, = 0) serial
SCHEN_B
port's channels A and B DMA chaining. Bits 19 and 21 apply to all oper-
ating modes.
Frame Sync Both Enable.
the SPORTS channels A and B are configured to transmit/receive data. If
set (= 1), this bit issues frame sync only when data is present in both trans-
mit buffers,
TXA
present in either transmit buffers. This bit applies to DSP Standard Serial
mode only.
When a SPORT is configured as a receiver, if
sync is issued only when both the Rx FIFOs (
full.
This bit is not used for I
channel A or channel B is selected, the frame sync behaves as if
cleared (= 0). If both A and B channels are selected, the word select acts as
if is set (= 1).
FS_BOTH
Buffer Hang Disable.
causes the processor core to hang when it attempts to write to a full buffer
or read from an empty buffer. When set (= 1), this bit disables the
core-hang. In this case, a core read from an empty receive buffer returns
previously-read (invalid) data and core writes to a full transmit buffer to
overwrite (valid) data that has not yet been transmitted. This bit is used in
all modes.
Data Direction Control.
data direction of the serial port channel A and B signals.
• 0 = SPORT is configured to receive on both channels A and B. In
this configuration, the
while the Receive Shift registers are controlled by
SPORTx_FS
9-56
bit 22 (
SPCTLx
and . If cleared (= 0), a frame sync is issued if data is
TXB
2
S and Left-justified Sample Pair modes. If only
bit 23 (BHD). When cleared (= 0), this bit
SPCTLx
bit 25 (
SPCTLx
RXSPxA
. The and
TXSPxA
ADSP-2126x SHARC Processor Hardware Reference
bits 19 and 21 (
SPCTLx
). This bit applies when
FS_BOTH
FS_BOTH
and
RXSPA
). This bit controls the
SPTRAN
and buffers are activated,
RXSPxB
buffers are inactive.
TXSPxB
and
SCHEN_A
is set (= 1), frame
) are not
RXSPB
is
FS_BOTH
and
SPORTx_CLK