Latching Interrupts - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Latching Interrupts

When the DSP recognizes an interrupt, the DSP's interrupt latch (
and ) registers set a bit (latch) to record that the interrupt occurred.
LIRPTL
The bits in these registers indicate all interrupts that are currently being
serviced or are pending. Because these registers are readable and writable,
any interrupt except reset (
in software.
When an interrupt occurs, the sequencer sets the corresponding bit in
or
IRPTL LIRPTL
of the interrupt's service routine, the DSP clears this bit during every
cycle. This prevents the same interrupt from being latched while its service
routine is executing. After the return from interrupt (
stops clearing the latch bit.
If necessary, an interrupt can be reused while it is being serviced. (This is a
matter of disabling this automatic clearing of the latch bit.)
information, see "Reusing Interrupts" on page 3-60.
The interrupt latch bits in
register. In both registers, the interrupt bits are arranged in order of
IMASK
priority. The interrupt priority is from 0 (highest) to 31 (lowest). Inter-
rupt priority determines which interrupt is serviced first when more than
one occurs in the same cycle. Priority also determines which interrupts are
nested when the DSP has interrupt nesting enabled.
tion, see "Nesting Interrupts" on page 3-58.
While the
IRPTL
register contains latch and mask bits for the
LIRPTL
, ,
MR1 GPTMR2 DAI
Several events can cause arithmetic interrupts. They are fixed-point over-
flow ( ) and floating-point overflow (
FIXI
invalid operation (
a program can read the arithmetic status flags in the
ADSP-2126x SHARC Processor Hardware Reference
) and emulator (
RSTI
once that interrupt is serviced. Throughout the execution
correspond to interrupt mask bits in the
IRPTL
register latches interrupts for a variety of events, the
(low priority),
SPI
). To determine which event caused the interrupt,
FLTII
Program Sequencer
) can be set or cleared
EMUI
RTI
For more informa-
SP0
(low priority) interrupts.
), underflow (
FLTOI
STKYx
IRPTL
), the sequencer
For more
, , , ,
SP2 SP4 PP GPT-
), and
FLTUI
or status
STKYy
3-55