Active State Multichannel Receive Frame Sync Select; Multichannel Mode Control Bits - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

The
SPORT0_FS
signal, which is active during transmission of an enabled word. Because
the serial port's
three-stated when the time slot is not active, the
SPORT0_FS/SPORT2_FS/SPORT4_FS
SPORT0_DA/B/SPORT2_DA/B/SPORT4_DA/B
The
SPORT0_FS
and the
TDV23
These signals become outputs. Do not connect
, and
SPORT0_FS
Bus contention between the transmit data valid and multichannel frame
sync signals will result.
After the
TXSPxA
,
SPORT0_FS SPORT2_FS/SPORT4_FS
DMA is used, this may occur several cycles after the multichannel trans-
mission is enabled. If a deterministic start time is required, pre-load the
transmit buffer.

Active State Multichannel Receive Frame Sync Select

The bit in the
LRFS
level of the multichannel received frame sync signals as active low
(inverted) if set (=1) or active high if cleared (=0). Active high (=0) is the
default.

Multichannel Mode Control Bits

Several bits in the
channel mode operation:
• Operation mode (
• Word length (
ADSP-2126x SHARC Processor Hardware Reference
, or
SPORT2_FS SPORT4_FS
,
SPORT0_DA/B SPORT2_DA/B
signal is renamed
signal is renamed
SPORT4_FS
(
SPORT4_FS TDV45
transmit buffer is loaded, transmission begins and the
,
SPCTL1 SPCTL3
Control register enable and configure multi-
SPCTLx
)
OPMODE
)
SLEN
is used as a transmit data valid
and
SPORT4_DA/B
signal specifies if
is being driven by the processor.
. The
TDV01 SPORT2_FS
in multichannel mode.
TDV45
SPORT2_FS
) to in multichannel mode.
SPORT1_FS
signal is generated. When serial port
, and registers selects the logic
SPCTL5
Serial Ports
signals are
signal is renamed
( ) to
TDV23
9-27