Data File Data Registers (Rx, Sx; Alternate Data File Data Registers (Rx', Sx - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Table A-6. Processing Element Registers
Register Name and Page Reference
"Data File Data Registers (Rx, Sx)" on page A-21
"PEx Multiplier Result Registers (MRFx, MRBx)" on page A-22
"Program Memory Bus Exchange Register (PX)" on page A-23

Data File Data Registers (Rx, Sx)

The Data File Data registers are non memory-mapped, universal, data reg-
isters ( and
Ureg
register file—a set of 40-bit data registers that transfer data between the
data buses and the computation units. These registers also provide local
storage for operands and results.
The and prefixes on register names do not effect the 32-bit or 40-bit
R S
data transfer; the naming convention determines how the ALU, multi-
plier, and shifter treat the data and determines which processing element's
data registers are being used. For more information on how to use these
registers, see "Data Register File" on page

Alternate Data File Data Registers (Rx', Sx')

The processor includes alternate register sets for all data registers to facili-
tate fast context switching. Bits in the
alternate registers become accessible. While inaccessible, the contents of
alternate registers are not affected by processor operations. Note that there
is an one cycle latency between writing to MODE1 and being able to
access an alternate register set.
ADSP-2126x SHARC Processor Hardware Reference
). Each of the DSP's processing elements has a data
Dreg
Registers Reference
Initialization After Reset
Undefined
Undefined
Undefined
2-38.
register control when
MODE1
A-21