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SPISTAT (0x1002)
Reserved
TXCOL
Transmit Collision Error
RXS
Data Buffer Status (read-only)
1=Full
0=Empty
ROVF
Reception Error (Overflow)
1=New Data Received with Full RXSPI Buffer
TXS
Data Buffer Status (read-only)
1=Full
0=Empty
Figure A-28. SPISTAT Register
Table A-25. SPISTAT Register Bits
Bit
Name
0
SPIF
1
MME
2
TUNF
ADSP-2126x SHARC Processor Hardware Reference
31 30 29 28 27 26
25
24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
15 14 13 12 11 10
9
0
0
0
0
0
0
0
Function
SPIRCV bits in SPICTL. Set to 1 when the
appropriate shift-register has completed shift-
ing in or out data.
Multimaster Error or Mode-fault Error. Set
when the processor is configured as the SPI
master and another device tries to become the
master by driving the
"Mode Fault Error (MME)" on page
Transmission Error (Underflow). Set when a
transmission occurred with no new data in the
TXSPI register. See
(TUNF)" on page
Registers Reference
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
signal low. See
SPIDS
10-40.
"Transmission Error Bit
10-41.
0
Reserved
0
0
SPIF
SPI Transmit Transfer
Complete
1=Transfer Complete
0=Transfer Active
MME
Multimaster Error
1=SPIDS Asserted by
Slave
0=No Error
TUNF
Transmission Error (Under-
flow)
1=No New Data in
TXSPI Buffer
Type
Default
RO
1
W1C
0
W1C
0
A-93
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