Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 716

I/O Processor Registers
Table A-25. SPISTAT Register Bits (Cont'd)
Bit Name
3 TXS
4 ROVF
5 RXS
6 TXCOL
31–7 Reserved
The transmit buffer is full after data is written to it and is empty when a
transfer begins and the transmit value loads into the Shift register. The
receive buffer is full at the end of a transfer when the Shift register value is
loaded into the receive buffer. It is empty when the receive buffer is read.
The SPI status also depends on the
packing is enabled, then the receive buffer status is set to full only after
two transfers from the Shift register.
A-94
Function
Transmit Data Buffer Status. Indicates the
TXSPI data buffer status.
0 = Empty
1 = Full
Reception Error (Overflow). Set when data is
received and the receive buffer is full.
1 = New data received with full RXSPI regis-
ter. See "Reception Error Bit (ROVF)" on
page 10-42.
Receive Data Buffer Status. Indicates the
RXSPI data buffer status.
0 = Empty
1 = Full
Transmission Collision Error. The TXCOL
flag is set in the SPISTAT register when a
write to the TXSPI register coincides with the
load of the shift register. See
sion Error Bit (TXCOL)" on page 10-42
PACKEN
ADSP-2126x SHARC Processor Hardware Reference
Type
RO
W1C
RO
W1C
"Transmit Colli-
bit in the
SPICTL
Default
0
0
0
0
register. If