Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 343

occurs on the external bus. For example, after the core reads the
TXPP
register, it will take some number N core-cycles for the PP to shift out that
data to the memory. During that time, the core can go on doing other
tasks. After N core-cycles have passed, the parallel port may be disabled
and the external address register updated for another access.
To determine the duration for each access, the designer simply add's the
number of data-cycles and the duration of each (measured in
along with the number of
This duration is deterministic, and is based on two settings in the
register—parallel port data-cycle duration (
Enable ( ).
PPBHC
Please refer to
allel port bus cycles, but in summary, programs can use the following
values:
• each
ALE
settings.
PPBHC
• each Data cycle is the setting in the
For example, in 8-bit mode, a single-word transfer is comprised of 1
cycle and 4 Data cycles. If
= 0, this transfer completes in:
PPBHC
(1 -cycle x 3
ALE
word.
This means that 15-instructions after data is written to
, the parallel port has finished writing/fetching that data externally,
RXPP
and the parallel port may be disabled. This case is shown in
page 8-27.
ADSP-2126x SHARC Processor Hardware Reference
cycles (which are fixed at 3
ALE
"Parallel Port Operation"
cycle is fixed at 3
PPDUR3
) + (4 data-cycles x 3
CCLK
) and Bus Hold Cycle
PPDUR
for further explanation of the par-
cycles, regardless of the
CCLK
register (+1 if
PPDUR
is used (the fastest case) and
) = 15 core cycles per 32-bit
CCLK
Parallel Port
PPTX
cycles)
CCLK
cycles).
CCLK
PPCTL
or
PPDUR
=1)
PPBHC
ALE
or read from
TXPP
Listing 8-3 on
8-21