Spi Enable; Open Drain Mode (Opd) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

is on a single node, and every
mission and reception are always enabled simultaneously, unless the
Broadcast mode has been selected. In Broadcast mode, several slaves can
be configured to receive, but only one of the slaves can be in Transmit
mode, driving the
can be ignored. This section describes the clock signals, SPI operation as a
master and as a slave, and error generation.

SPI Enable

When the SPI is disabled (
selects ( –
FLG0
and no data transfers will occur. For slaves, the slave-select input acts like
a reset for the internal SPI logic.

When the
shuts down the clock to the SPI), the
the
FLGS7–0
with the clock.
For this reason, the
also be used as a software reset of the internal SPI logic. An exception to
this is the W1C-type (write 1-to-clear) bits in the
will remain set if they are already set. For a list of write 1 to-clear-bits.

Always clear the W1C-type bits before re-enabling the SPI, as these
bits will not get cleared even if SPI is disabled. This can be done by
writing 0xFF to the
enable the SPI port after

Open Drain Mode (OPD)

In a multimaster or multislave SPI system, the data output pins (
) can be configured to behave as open drain drivers to prevent
MISO
contention and possible damage to pin drivers. An external pull-up
10-8
SPICLK
line. If the transmit or receive is not needed,
MISO
SPIEN
) are controlled by the general-purpose flag I/O module,
FLG3
bit (bit 30 in the
SPIPDN
register bits) because the
line must be error free. The
SPIDS
SPISTAT
ADSP-2126x SHARC Processor Hardware Reference
pin should be connected. SPI trans-
= 0), the flag pins used as slave device
register) is set (= 1 which
PMCTL
FLGx
FLGx
register. In the case of an
is deasserted.
SPIDS
pins cannot be used (via
pins are synchronized
signal can
SPIEN
Status register
SPISTAT
error,
MME
MOSI
MISO
and