Fifo Control And Status - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

FIFO Control and Status

FIFO Control and Status
Several bits can be used to control and monitor FIFO operations:
• IDP Enable. The
enables the IDP.
• IDP Buffer Hang Disable. The
register) determines whether or not the core hangs on reads when
the FIFO is empty.
• Number of Samples in FIFO. The
the
DAI_STAT
the FIFO.
• FIFO Overflow Status. The
DAI_STAT
• FIFO Overflow Clear bit. The
IDP_CTL
The IDP is enabled through the
the IDP is enabled. When this bit is cleared (= 0), the IDP is disabled, and
data can not come to the
this bit transitions from 1 to 0, all data in the IDP FIFO is cleared.
The bit is used for buffer hang disable control. When there is no
IDP_BHD
data in the FIFO, reading the
This condition continues until the FIFO contains valid data. Setting the
bit (= 1) prevents the core from hanging on reads from an empty
IDP_BHD
register. Clearing this bit (= 0) causes the core to hang under the
IDP_FIFO
conditions described previously.
The
IDP_FIFOSZ
four-bit field identifies the number of valid data samples in the IDP
FIFO.
11-14
IDP_ENABLE
register) monitors the number of valid data words in
register) monitors overflow error conditions in the FIFO.
register) clears an indicated FIFO overflow error.
IDP_ENABLE
IDP_FIFO
IDP_FIFO
bits track the number of words in the FIFO. This
ADSP-2126x SHARC Processor Hardware Reference
bit (bit 7 of the
bit (bit 4 in the
IDP_BHD
IDP_FIFOSZ
bit (bit 25 in the
IDP_FIFO_OVER
bit (bit 6 of the
IDP_CLROVR
bit. When this bit is set (= 1),
register from the IDP channels. When
register causes the core to hang.
register)
IDP_CTL
IDP_CTL
bits (bits 31–28 in