Dags, Registers, And Memory; Dag Register-To-Bus Alignment - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

DAGs, Registers, and Memory

DAG registers are part of the DSP's universal register (
may load the DAG registers from memory, from another universal regis-
ter, or with an immediate value. Programs may store DAG registers'
contents to memory or to another universal register.
The DAG's registers support the bidirectional register-to-register transfers
that are described in
When the DAG register is a source of the transfer, the destination can be a
register file data register. This transfer results in the contents of the single
source register being duplicated in complementary data registers in each
processing element.
Programs should use care in the case where the DAG register is a destina-
tion of a transfer from a register file data register source. Programs should
use a conditional operation to select either one processing element or nei-
ther as the source. Having both processing elements contribute a source
value results in the PEx element's write having precedence over the PEy
element's write.
In the case where a DAG register is both source and destination, the data
move operation executes the same as it would if SIMD mode were dis-
abled ( cleared).
PEYEN

DAG Register-to-Bus Alignment

There are three word alignment types for DAG registers and PM or DM
data buses: normal word, extended-precision normal word, and long
word.
The DAGs align normal word (32-bit) addressed transfers to the low order
bits of the buses. These transfers between memory and 32-bit DAG1 or
DAG2 registers use the 64-bit DM and PM data buses.
trates these transfers.
ADSP-2126x SHARC Processor Hardware Reference
"SIMD (Computational) Operations" on page
Data Address Generators
) set. Programs
Ureg
Figure 4-5
2-50.
illus-
4-19