Emulation Registers; Hardware Breakpoint Control Register (Brkctl - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Core Registers
Table A-15. SYSCTL Register Bit Descriptions (Cont'd)
Bits Name
20 PPFLGS
31–21 Reserved

Emulation Registers

The following sections describe the emulation registers.

Hardware Breakpoint Control Register (BRKCTL)

The register controls how breakpoints are used (if the
BRKCTL
set). This user-accessible register in the
.
0x30025
The register is a 32-bit memory-mapped I/O register. The proces-
BRKCTL
sor core can write into this register. The bits related to the breakpoint
register are same as in the
A-46
Definition
Parallel Port Select.
0 = Parallel port is selected.
1 = Parallel port is not selected. ADDR and DATA pins are in
FLAG mode. Permits core writes. Configuring the parallel port
pins to function as FLAG0-15 also causes the FLAG[0:3] pins to
change to their alternate role,
register.
EMUCTL
ADSP-2126x SHARC Processor Hardware Reference
and TIMEXP.
IRQ0-2
register is located at address
BRKCTL
bit is
UMODE