Sport Transmit Compand Registers (Mtxccsy; Sport Receive Select Registers - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

I/O Processor Registers

SPORT Transmit Compand Registers (MTxCCSy)

The addresses of the
MT0CCS0 – 0xC0D
MT0CCS2 – 0xC0F
MT2CCS0 – 0x40D
MT2CCS2 – 0x40F
MT4CCS0 – 0x80D
MT4CCS2 – 0x80F
The reset value for these registers is undefined.
Each bit, 31–0, set (= 1) in one of four
companded transmit channel, 127–0, on a Multichannel mode serial port.
When the
MTxCCSy
port applies the companding from the serial port's
transmitted word in that channel's position of the data stream. When a
channel's bit in the
not compand the output during the channel's receive time slot.
SPORT Receive Select Registers (MRxCSy
The addresses of the
MR1CS0 – 0xC09
MR1CS2 – 0xC0B
MR3CS0 – 0x409
MR3CS2 – 0x40B
MR5CS0 – 0x809
MR5CS2 – 0x80B
The reset value for these registers is undefined.
A-88
registers are:
MTxCCSy
MT0CCS1 – 0xC0E
MT0CCS3 – 0xc10
MT2CCS1 – 0x40E
MT2CCS3 – 0x410
MT4CCS1 – 0x80E
MT4CCS3 – 0x810
register activates companding for a channel, the serial
register is cleared (= 0), the serial port does
MTxCCSy
registers are:
MRxCSx
MR1CS1 – 0xC0A
MR1CS3 – 0xC0C
MR3CS1 – 0x40A
MR3CS3 – 0x40C
MR5CS1 – 0x80A
MR5CS3 – 0x80C
ADSP-2126x SHARC Processor Hardware Reference
registers corresponds to an
MTxCCSy
DTYPE
selection to the