Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 819

EMPP register, 8-17, 15-22,
EMUCLKx register, 6-4,
EMUI (emulator lower priority interrupt)
bit, A-28, A-29
emulation (JTAG), 1-2
emulator
clock See EMUCLKx register
control shift (EMUCTL) register,
enable (EMUENA) bit,
interrupt (EMUI) bit, A-28,
interrupt enable (EIRQENA) bit,
emulator clock See EMUCLKx register
emulator control shift (EMUCTL) register,
A-51
emulator idle (EMUIDLE) instruction,
emulator lower priority interrupt (EMUI),
A-28, A-29
emulator Nth event counter See EMUN
register
EMUN register, 6-4
EMUPID, 6-5
enable
breakpoint (ENBx) bit,
breakpoints (ENBx) bit,
(BRKOUT) pin, A-51
DMA interrupt on transfer See INTEN
bit
DMA interrupt See INTEN bit
interrupt on error See INTERR bit
master input slave output See EMISO bit
SPI DMA, 10-46
SPIDS See ISSEN bit
enabling
DMA, 11-18
SPORT DMA (SDEN),
SPORT master mode (MSTR),
ADSP-2126x SHARC Processor Hardware Reference
A-113
6-9
A-51
A-51
A-29
A-51
6-9
A-52
A-50
9-23
9-21
endian format, 9-40, G-4
end-of-loop instruction address,
enhanced emulation
feature enable (EEMUENS) bit,
features and bits (EEMUENS)
FIFO status (EEMUOUTFULLS) bit,
A-60
INDATA FIFO status
(EEMUINFULLS) bit, A-57,
OUTDATA FIFO status
(EEMUOUTFULLS) bit,
OUTDATA interrupt enable
(EEMUOUIRQENS) bit,
OUTDATA ready (EEMUOUTRDY)
bit, A-60
Equals (EQ) condition,
errors/flags See DMA, external port, host
port, serial port, SPI port, and UART
port
examples
bit reverse addressing,
cache inefficient code,
direct branch, 3-12
DO UNTIL loop, 3-25
interrupt service routine,
long word moves, 5-24
PX register transfers,
single and dual data access,
examples, timing
framed vs. unframed data,
left-justified sample pair mode,
normal vs. alternate framing,
serial port word select,
execute address latency in PC register,
execute cycle, 3-4
explicit versus implicit operations,
Index
3-27
A-61
A-60
A-60
A-60
3-19
4-8
3-10
3-60
5-6 to 5-9
5-29
9-37
9-17
9-37
9-23
3-64
G-4
I-9