Fifo To Memory Data Transfer - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

The
IDP_FIFO_OVER
This bit is set (= 1), whenever an overflow occurs. When this bit is cleared
(= 0), it indicates there is no overflow condition. This read-only bit is a
sticky bit, which does not automatically reset to 0 when it is no longer in
overflow condition. This bit must be reset manually, using the
bit in the
IDP_CTL
dition in the
DAI_STAT
always returns

FIFO to Memory Data Transfer

The data from each of the eight IDP channels is inserted into an eight reg-
ister deep FIFO, which can only be transferred to the core's memory space
sequentially. Data is moved into the FIFO as soon as it is fully received.
When more than one channel has data ready, the channels access the
FIFO with fixed priority, from low to high channel number (that is, chan-
nel 0 is the highest priority and channel 7 is the lowest priority).
One of two methods can be used to move data from the IDP FIFO to
internal memory:
• The core can remove data from the FIFO manually by reading the
memory-mapped register,
held in the (read-only)
read, the corresponding element is removed from the IDP FIFO,
and the next element is moved into the
anism is provided to generate an interrupt when more than a
specified number of words are in the FIFO. This interrupt signals
the core to read the
This method of moving data from the IDP FIFO is described in
"Interrupt-Driven Transfers" on page
ADSP-2126x SHARC Processor Hardware Reference
bit provides IDP FIFO overflow status information.
register. Writing one to this bit clears the overflow con-
register. Since
when read.
LOW
IDP_FIFO
IDP_FIFO
is a write-only bit, it
IDP_CLROVR
. The output of the FIFO is
IDP_FIFO
register. When this register is
IDP_FIFO
register.
11-16.
Input Data Port
IDP_CLROVR
register. A mech-
11-15