Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 449

The SPI port supports both Master mode and Slave mode DMA. The fol-
lowing sections describe Slave and Master mode DMA operation, DMA
chaining, switching between transmit and receive DMA operations, and
processing DMA interrupt errors.

Do not write to the
DMA operation because DMA data will be overwritten. However,
writes to the
ation are permitted. The
register is read. Reads from the
time during transmit DMA. Interrupts are generated based on
DMA events and are configured in the
Similarly, do not read from the
DMA receive operations.
In order for a transmit DMA operation to begin, the transmit buffer must
initially be empty (
that the
TXSPI
transfers. For example, the
register for temporary data storage. Writing to the
software sets the
When the SPI DMA engine is configured for transmitting:
1. The receive interface cannot generate an interrupt, but the status
can be polled.
2. The four-deep FIFO is not available in the receive path.
Similarly, when the SPI DMA engine is configured for receiving,
1. The transmit interface cannot generate an interrupt, but the status
can be polled.
2. The four-deep FIFO is not available in the transmit path.
ADSP-2126x SHARC Processor Hardware Reference
TXSPI
register during an active SPI receive DMA oper-
TXSPI
RXS
= 0). While this is normally the case, this means
TXS
register should not be used for any purpose other than SPI
TXSPI
bit.
TXS
Serial Peripheral Interface Port
register during an active SPI transmit
register is cleared when the
register are allowed at any
RXSPI
SPIDMAC
register during active SPI
RXSPI
register should not be used as a scratch
TXSPI
RXSPI
register.
register via the
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