Dual Alternate Registers; Simd And Status Flags; Simd (Computational) Operations - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Secondary Processing Element (PEy)

Dual Alternate Registers

Both register files consist of a primary set of 16 by 40-bit registers and an
alternate set of 16 by 40-bit registers. Context switching between the two
sets of registers occurs in parallel between the two processing elements.
For more information, see "Alternate (Secondary) Data Registers" on
page 2-40.

SIMD and Status Flags

When the DSP is in SIMD mode (
processing elements generate status flags, producing a logical ORing of the
exception status test on each processing element. If one of the four
fixed-point or floating-point exceptions is enabled, an exception condition
on either or both processing elements generates an exception interrupt.
Interrupt service routines (ISRs) must determine which of the processing
elements encountered the exception.
Note that returning from a floating-point interrupt does not automatically
clear the
STKY
ment's sticky status (
service routine.

SIMD (Computational) Operations

In SIMD mode, the dual processing elements execute the same instruc-
tion, but operate on different data. To support SIMD operation, the
elements support a variety of dual data move features.
The DSP supports unidirectional and bidirectional register-to-register
transfers with the Conditional Compute and Move instruction. All four
combinations of inter-register file and intra-register file transfers

(PEx PEx, PEx
both SISD (unidirectional) and SIMD (bidirectional) modes.
2-50
state. Code must clear the
and
STKYx STKYy
"Interrupts and Sequencing" on page
 
PEy, PEy
ADSP-2126x SHARC Processor Hardware Reference
bit=1), computations on both
PEYEN
bits in both processing ele-
STKY
) registers as part of the exception

PEx, and PEy PEy) are possible in
3-48.