Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 806

Interleaved data. To take advantage of the DSP's data accesses to 4- and
3-column locations, programs must adjust the interleaving of data into
(not necessarily sequential) memory locations to accommodate the mem-
ory access mode.
Internal memory space. This space ranges from address 0x0000 0000
through 0x0005 3FFF (Normal word). Internal memory space refers to
the DSP's on-chip SRAM and memory mapped registers.
Interrupts. Subroutines in which a runtime event (not an instruction)
triggers the execution of the routine.
JTAG port. This port supports the IEEE standard 1149.1 Joint Test
Action Group (JTAG) standard for system test. This standard defines a
method for serially scanning the I/O status of each component in a
system.
Jumps. Program flow transfers permanently to another part of program
memory.
Length registers. A length registers is a Data Address Generator (DAG)
register that sets up the range of addresses a circular buffer.
Level-sensitive interrupts. The DSP detects this type of interrupt if the
signal input is low (active) when sampled on the rising edge of CLKIN.
Loops. One sequence of instructions executes several times with zero
overhead.
McBSP, Multichannel buffered serial port. See Serial port.
MCM, Multichannel mode. See Multichannel mode on page G-10.
Memory Access Modes. The DSP supports Asynchronous external mem-
ory space. In asynchronous access mode, the DSP's RD and WR strobes
change before CLKIN edge. In synchronous access mode, the DSP's RD
and WR strobes change on CLKIN edge.
G-6 ADSP-2126x SHARC Processor Core Manual