Parallel Port Booting - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Table 15-6. Booting Modes
BOOT_CFG1-0
00
01
10
11

Parallel Port Booting

The ADSP-2126x supports an 8-bit boot mode through the parallel port.
This mode is used to boot from external 8-bit wide memory devices. The
processor is configured for 8-bit boot mode when the
pins = 10. When configured for parallel boot loading, the
BOOT_CFG1–0
parallel port transfers occur with the default bit settings (shown in
Table 15-7) for the
Table 15-7. Parallel Port Boot Mode Settings in the PPCTL
Register
Bit
PPALEPL
PPEN
PPDUR
PPBHC
PP16
PPDEN
PPTRAN
PPBHD
ADSP-2126x SHARC Processor Hardware Reference
Description
SPI Slave boot
SPI Master boot
EPROM boot via parallel port
ROM Boot mode (not available on all
ADSP-2126x processors)
register.
PPCTL
Setting
= 0; ALE is active high
= 1
= 10111; (24 core clock cycles per data transfer cycle)
= 1; insert a bus hold cycle on every access
= 0; external data width = 8 bits
= 1; use DMA
= 0; receive (read) DMA
= 0; buffer hang enabled
System Design
15-21