Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 844

Index
TMSTAT (timer status) register,
TMS (test mode select) pin,
TMxCNT (timer count) register,
TMxCTL (peripheral timer control)
registers, A-158
TMxCTL (timer configuration) registers,
14-1
TMxSTAT (peripheral timer status)
register, A-159
TMZHI (timer expired high priority) bit,
A-28
TMZHI (timer expired HI priority) bit,
3-47
TMZLI (timer expired LO priority) bit,
3-47
TMZLI (timer expired low priority) bit,
A-29
toggle, bit, 2-30
tools, development, 1-13
top-of-loop address, 3-26
top-of-PC stack, 3-17
TPERIOD register, A-36
TPERIOD (timer period) register,
T_PRDHx registers, 14-1
transfer control block (TCB), 7-13,
transfer data buffer status See TXS bit
transfer initiation and interrupt See
TIMOD mode
transfer protocol, 8-8
transmission collision error See TXCOL bit
transmission error See TUNF bit
transmit and receive channel order (FRFS),
selecting, 9-16
transmit and receive data buffers
(TXSPxA/B, RXSPxA/B),
transmit buffers, 9-60
transmit collision error See TXCOL bit
transmit data, serial port See TXSPx
registers
transmit data buffer status See TXS bit
I-34
14-3
6-1
14-1
3-46
G-10
9-60
ADSP-2126x SHARC Processor Hardware Reference
transmit data See TXSPI buffer
transmit frame sync divisor See TFSDIV bit
transmit shift See TXSR register
Transmit Shift (TXSR) register, 10-2,
A-100
TRST pin, 6-1, 15-12
True always (TRUE) if condition,
truncate, rounding See TRUNC bit
truncate, rounding (TRUNC) bit,
TRUNC bit, 2-12
TUNF bit, 10-41, A-93
TUVF_A bit, 9-30, 9-57, 9-58,
T_WHRx registers, 14-1
twos-complement data, 2-15,
TX2A register, 9-46
TXCOL bit, 10-42, A-94
TXFLSH bit, 10-22, A-99
TXFLSH (flush transmit buffer) bit,
TXPP register, A-111
TXS bit, 9-59, 10-29,
TXSP0A register, 9-50
TXSP1A register, 9-50
TXSP3A register, 9-46
TXSP4A register, 9-48
TXSP5A register, 9-48
TXSPI register, 7-23, 10-9, 10-12, 10-37,
10-38, 10-41, A-93, A-100,
TXSPI (SPI transmit buffer) register,
TXSPxB register, 9-46, 9-47, 9-48,
TXSPx registers, 7-23,
TXSR register, 10-2, A-100
TXx registers, A-85
U
U64MA bit, 5-21, 5-28, A-9,
UMODE bit, A-46, A-54
unaligned 64-bit memory access (U64MA)
bit, A-9
uncomplemented register,
underflow exception, 2-13
3-20
A-6
A-78
2-18
10-51
A-94
A-101
10-43
9-50
A-85
A-19
3-37