Dag Register Transfer Restrictions - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

64-bit bus, and the odd numbered register – 1 value (
example) transfers on the upper half (bits 63-32) of the bus.
In both the even and odd numbered cases, the explicitly specified DAG
register sources or sinks bits 31-0 of the long word addressed memory.
63
31
IMPLICIT (NAMED + OR - 1)
DAG1 OR DAG2 REGISTERS
Figure 4-7. Long Word DAG Register-to-Data Register Transfers
For implicit moves and long word accesses that use the
example:
equates to
I0 = PX;
only the contents of the
lowing example:
equates to
PX = I0;

DAG Register Transfer Restrictions

The two types of transfer restrictions are hold-off conditions and illegal
conditions that the DSP does not detect.
For certain instruction sequences involving transfers to and from DAG
registers, an extra (
case where an instruction that loads a DAG register is followed by an
instruction that uses any register in the same DAG register pair
addressing, modify instructions, or indirect jumps, the DSP inserts an
extra ( ) cycle between the two instructions. This hold-off occurs
NOP
ADSP-2126x SHARC Processor Hardware Reference
DM OR PM DATA BUS
31
0 31
I0 = PX1;
register are written into I0. However, the fol-
PX1
PX1 = PX2 = I0;
) cycle is automatically inserted by the processor. In
NOP
Data Address Generators
I0
EXPLICIT (NAMED)
DAG1 OR DAG2 REGISTERS
.
or in this
B2
0
0
registers, as for
PX
1
for data
4-21