Timer Status And Control - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

through the
TMxPRD[30:0]
both. Assuming
maximum period = 2 x (2

Timer Status and Control

The Timer Global Status and Control (
tus of all three timers using a single read. The
timer enable bits. Within
bits, that require a write one-to-set (
( ) to enable and disable the timer respectively.
TIMxDIS

Writing a one to both bits of a pair disables that timer.
Each timer also has an Overflow Error Detection bit,
overflow error occurs, this bit is set in the
write one-to-clear this bit.
See Table 14-1
ADSP-2126x SHARC Processor Hardware Reference
and the
= 200 MHz:
CCLK
31
– 1) x 5 ns = 20 seconds.
, each timer has a pair of sticky Status
TMSTAT
for more information about bits in the
bits. Bit 31 is ignored for
TMxW[30:0]
) register indicates the sta-
TMSTAT
register also contains
TMSTAT
) or write one-to-clear
TIMxEN
register. A program must
TMSTAT
Peripheral Timer
. When an
TIMxOVF
register.
TMSTAT
14-3