Spi Baud Rate Register (Spibaud) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

I/O Processor Registers

SPI Baud Rate Register (SPIBAUD)

The SPI Baud Rate register's address is 0x1005 and its reset value is unde-
fined. This SPI register is a 16-bit read-write register that is used to set the
bit transfer rate for a master device. When configured as a slave, the value
written to this register is ignored. The
written at any time.
Writing a value of zero or one to the register disables the serial clock.
Therefore, the maximum serial clock rate is one-fourth the core clock rate
( ).
CCLK
Table A-28. SPIBAUD Register Bit Descriptions
Bits Name
0 Reserved
15–1 BAUDR
31–16 Reserved
Table A-29. SPI Master Baud Rate Example
BAUDR
(Decimal Value)
0
1
2
3
4
32,767, (0x7FFF)
A-102
Definition
Enables the SPICLK per the following equation:
SPICLK baud rate = core clock (CCLK)/4 x BAUDR)
Default = 0.
SPI Clock Divide Factor
N/A
4
8
12
16
131,068
ADSP-2126x SHARC Processor Hardware Reference
register can be read or
SPIBAUD
Baud Rate for CCLK @ 200 MHz
N/A
50.0 MHz
25.0 MHz
16.67 MHz
12.5 MHz
1.53 KHz