Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 567

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frame sync generated in this example is set for a 50% duty cycle, with no

phase shift.

Listing 13-1. PCG Channel B Output Example

/* Register definitions */

#define SRU_CLK3

#define SRU_PIN0

#define SRU_PBEN0

#define PCG_CTLB1

#define PCG_CTLB0

#define PCG_PW

/* SRU definitions */

#define PCG_CLKB_P

#define PCG_FSB_P

#define PBEN_HIGH_Of

//Bit Positions

#define DAI_PB02

#define PCG_PWB

/* Bit definitions */

#define ENFSB

#define ENCLKB

/* Main code section */

.global _main;

.section/pm seg_pmco;

/* Route PCG Channel B clock to DAI Pin 1 via SRU */

/* Route PCG Channel B frame sync to DAI Pin 2 via SRU */

r0 = PCG_CLKB_P|(PCG_FSB_P<<DAI_PB02);

dm(SRU_PIN0) = r0;

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