Slave Mode Core Transfers - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Programming Model
If the transmit buffer remains empty, or the receive buffer remains full,
the device operates according to the states of the
registers.
SPICTLx
• If
SENDZ
transmits zeros on the
new transfer initiate command.
• If
SENDZ
transmits the last word transmitted before the transmit buffer
became empty.
• If = 1 and the receive buffer is full, the device continues to
GM
receive new data from the
the
RXSPI
• If = 0 and the receive buffer is full, the incoming data is dis-
GM
carded, and the

Slave Mode Core Transfers

When a device is enabled as a slave (and DMA mode is not selected), the
start of a transfer is triggered by a transition of the
the active state (
depending on the state of
The following steps illustrate SPI operation in slave mode.
1. Write to the
the same as the mode that is set up in the SPI master.
2. Write the data to be transmitted into the
pare for the data transfer.
3. Once the
sending and receiving data on active
10-44
= 1 and the transmit buffer is empty, the device repeatedly
MOSI
= 0 and the transmit buffer is empty, the device repeatedly
MISO
buffer.
register is not updated.
RXSPI
) or by the first active edge of the clock (
LOW
.
CPHASE
registers to make the mode of the serial link
SPICTLx
signal's falling edge is detected, the slave starts
SPIDS
ADSP-2126x SHARC Processor Hardware Reference
SENDZ
pin. One word is transmitted for each
pin, overwriting the older data in
SPIDS
TXSPIx
edges.
SPICLK
and bits in the
GM
select signal to
),
SPICLK
registers to pre-